diff options
| author |   Jesse Barnes <jbarnes@virtuousgeek.org> | 2010-04-21 11:39:23 -0700 |
|---|---|---|
| committer |   Eric Anholt <eric@anholt.net> | 2010-04-22 14:48:55 -0700 |
| commit | e552eb7038a36d9b18860f525aa02875e313fe16 (patch) | |
| tree | bcbab5ec16994d6747794bab8f4bc38780f0157f /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: cleanup FBC buffers at unload time (diff) | |
| download | linux-dev-e552eb7038a36d9b18860f525aa02875e313fe16.tar.xz linux-dev-e552eb7038a36d9b18860f525aa02875e313fe16.zip | |
drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge
Since 965, the hardware has supported the PIPE_CONTROL command, which
provides fine grained GPU cache flushing control. On recent chipsets,
this instruction is required for reliable interrupt and sequence number
reporting in the driver.
So add support for this instruction, including workarounds, on Ironlake
and Sandy Bridge hardware.
https://bugs.freedesktop.org/show_bug.cgi?id=27108
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 773c1adb2541..4cbc5210fd30 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -230,6 +230,16 @@ #define ASYNC_FLIP (1<<22) #define DISPLAY_PLANE_A (0<<20) #define DISPLAY_PLANE_B (1<<20) +#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2) +#define PIPE_CONTROL_QW_WRITE (1<<14) +#define PIPE_CONTROL_DEPTH_STALL (1<<13) +#define PIPE_CONTROL_WC_FLUSH (1<<12) +#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */ +#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */ +#define PIPE_CONTROL_ISP_DIS (1<<9) +#define PIPE_CONTROL_NOTIFY (1<<8) +#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ +#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */ /* * Fence registers @@ -2285,6 +2295,7 @@ #define DEIER 0x4400c /* GT interrupt */ +#define GT_PIPE_NOTIFY (1 << 4) #define GT_SYNC_STATUS (1 << 2) #define GT_USER_INTERRUPT (1 << 0) |