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authorMatt Roper <matthew.d.roper@intel.com>2019-12-23 17:20:26 -0800
committerMatt Roper <matthew.d.roper@intel.com>2019-12-27 10:46:39 -0800
commit4ca153827f65a6779392fff668c46f9cc54d414b (patch)
tree12caa4d3bfd9bddfba3111ee67018618d939b6db /drivers/gpu/drm/i915/i915_reg.h
parentdrm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl (diff)
downloadlinux-dev-4ca153827f65a6779392fff668c46f9cc54d414b.tar.xz
linux-dev-4ca153827f65a6779392fff668c46f9cc54d414b.zip
drm/i915/tgl: Extend Wa_1408615072 to tgl
Although the workaround number and description are the same, the vsunit clock gate disable bit has moved to a new register and location on gen12. Bspec: 52890 Bspec: 52758 Cc: stable@kernel.vger.org Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191224012026.3157766-4-matthew.d.roper@intel.com Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 968a43f7cd98..030a3f3e69af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4181,6 +4181,9 @@ enum {
#define HSUNIT_CLKGATE_DIS REG_BIT(8)
#define VSUNIT_CLKGATE_DIS REG_BIT(3)
+#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
+#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
+
#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
#define CGPSF_CLKGATE_DIS (1 << 3)