aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/i915_reg.h
diff options
context:
space:
mode:
authorVandana Kannan <vandana.kannan@intel.com>2015-02-13 15:33:01 +0530
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-02-24 11:51:37 +0100
commit6fa7aec1db07f43d3ad94122c3bd52647c81619e (patch)
treef5798abe1993c32ee66760c0f10bd23e56112e9b /drivers/gpu/drm/i915/i915_reg.h
parentdrm/i915/bdw: Add support for DRRS to switch RR (diff)
downloadlinux-dev-6fa7aec1db07f43d3ad94122c3bd52647c81619e.tar.xz
linux-dev-6fa7aec1db07f43d3ad94122c3bd52647c81619e.zip
drm/i915: Support for RR switching on VLV
Definition of VLV RR switch bit and corresponding toggling in set_drrs function. Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2124119692d..55143cb36e74 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3916,6 +3916,7 @@ enum skl_disp_power_wells {
#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
+#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
#define PIPECONF_BPC_MASK (0x7 << 5)
#define PIPECONF_8BPC (0<<5)