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authorVandana Kannan <vandana.kannan@intel.com>2015-02-13 15:33:00 +0530
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-02-24 11:51:37 +0100
commita4c30b1d108c1ef60667ed357af4aeabc3d05eca (patch)
tree70150e9b9985ea8c35ca8aeba46aaf1ade1a27f7 /drivers/gpu/drm/i915/i915_reg.h
parentdrm/i915: Add support for DRRS in intel_dp_set_m_n (diff)
downloadlinux-dev-a4c30b1d108c1ef60667ed357af4aeabc3d05eca.tar.xz
linux-dev-a4c30b1d108c1ef60667ed357af4aeabc3d05eca.zip
drm/i915/bdw: Add support for DRRS to switch RR
For Broadwell, there is one instance of Transcoder MN values per transcoder. For dynamic switching between multiple refreshr rates, M/N values may be reprogrammed on the fly. Link N programming triggers update of all data and link M & N registers and the new M/N values will be used in the next frame that is output. V2: [By Ram]: intel_dp_set_m_n() is rewritten to accommodate gen >= 8 [Rodrigo] V3: Coding style correction [Ram] V4: [By Ram] intel_dp_set_m_n modifications are moved into a separate patch, retaining only DRRS related changes here [Rodrigo] Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Signed-off-by: Pradeep Bhat <pradeep.bhat@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
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