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| author |   Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2019-06-02 01:58:45 +0300 |
|---|---|---|
| committer | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2019-06-10 11:48:24 +0300 |
| commit | bf210f6c9e6fd8dc0d154ad18f741f20e64a3fce (patch) | |
| tree | 1e38e98c1d0f8fca686db81592a74ba9b8e66623 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | drm/i915: Move i915_check_and_clear_faults to intel_reset.c (diff) | |
| download | linux-dev-bf210f6c9e6fd8dc0d154ad18f741f20e64a3fce.tar.xz linux-dev-bf210f6c9e6fd8dc0d154ad18f741f20e64a3fce.zip | |
drm/i915/perf: fix whitelist on Gen10+
Gen10 added an additional NOA_WRITE register (high bits) and we forgot
to whitelist it for userspace.
Fixes: 95690a02fb5d96 ("drm/i915/perf: enable perf support on CNL")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190601225845.12600-1-lionel.g.landwerlin@intel.com
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dcf3c4d8d827..c87d288abb19 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1063,6 +1063,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define NOA_DATA _MMIO(0x986C) #define NOA_WRITE _MMIO(0x9888) +#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884) #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 |