path: root/drivers/gpu/drm/i915/intel_display.c
diff options
authorDurgadoss R <durgadoss.r@intel.com>2015-02-13 15:33:02 +0530
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-02-24 11:51:38 +0100
commit44395bfe2f2a22ec769eb51ea1908082cf9aa16d (patch)
tree24399eb6afe56a9a213fab97f9d85c165e2a6d01 /drivers/gpu/drm/i915/intel_display.c
parentdrm/i915: Support for RR switching on VLV (diff)
drm/i915: Enable eDP DRRS for CHV
This patch enables eDP DRRS for CHV by adding the required IS_CHERRYVIEW() checks. CHV uses the same register bit as VLV. [Vandana]: Since CHV has 2 sets of M_N registers, it will follow the same code path as gen < 8. Added CHV check in dp_set_m_n() [Ram]: Rebased on top of previous patch modifications Signed-off-by: Durgadoss R <durgadoss.r@intel.com> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ebb725851998..2ac93909cfc5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5879,7 +5879,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
* for gen < 8) and if DRRS is supported (to make sure the
* registers are not unnecessarily accessed).
- if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
+ if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
crtc->config->has_drrs) {
TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);