diff options
| author |   Damien Lespiau <damien.lespiau@intel.com> | 2014-12-12 14:26:58 +0000 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-12-15 15:43:18 +0100 |
| commit | c86ea3d0ad7e60fb92e3d4a0aa4906ec2868a7cd (patch) | |
| tree | 9a0afbfede019a0a018f3cda847f37839ddd6231 /drivers/gpu/drm/i915/intel_dp.c | |
| parent | drm/i915: Consolidate DDI clock reading out in a single function (diff) | |
| download | linux-dev-c86ea3d0ad7e60fb92e3d4a0aa4906ec2868a7cd.tar.xz linux-dev-c86ea3d0ad7e60fb92e3d4a0aa4906ec2868a7cd.zip | |
drm/i915/skl: Skylake also supports DP MST
I've checked that TRANS_DDI_MODE, DP_TP_CTL MST bits are identical to
HSW/BDW on SKL, as well as the long vs short HPD bits. So we have a good
chance to be working as well as prevous platforms.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3fc329682527..8e276c41d4d2 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5085,7 +5085,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp_aux_init(intel_dp, intel_connector); /* init MST on ports that can support it */ - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { + if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { if (port == PORT_B || port == PORT_C || port == PORT_D) { intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id); |