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| author |   Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-05-21 17:25:48 -0700 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-06-14 14:54:39 -0700 |
| commit | 1fa11ee2d9d0ccd58a6b56a9e490e336c99e98bf (patch) | |
| tree | b733f213d2b9bd106bade944beed00c286e92827 /drivers/gpu/drm/i915/intel_dpll_mgr.h | |
| parent | drm/i915/icl: unconditionally init DDI for every port (diff) | |
| download | linux-dev-1fa11ee2d9d0ccd58a6b56a9e490e336c99e98bf.tar.xz linux-dev-1fa11ee2d9d0ccd58a6b56a9e490e336c99e98bf.zip | |
drm/i915/icl: start adding the TBT pll
This commit just adds the register addresses and the basic skeleton of
the code. The next commits will expand on more specific functions.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-15-paulo.r.zanoni@intel.com
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dpll_mgr.h | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h index 78915057d2e6..ba925c7ee482 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h @@ -114,23 +114,27 @@ enum intel_dpll_id { */ DPLL_ID_ICL_DPLL1 = 1, /** + * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL + */ + DPLL_ID_ICL_TBTPLL = 2, + /** * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C) */ - DPLL_ID_ICL_MGPLL1 = 2, + DPLL_ID_ICL_MGPLL1 = 3, /** * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) */ - DPLL_ID_ICL_MGPLL2 = 3, + DPLL_ID_ICL_MGPLL2 = 4, /** * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) */ - DPLL_ID_ICL_MGPLL3 = 4, + DPLL_ID_ICL_MGPLL3 = 5, /** * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) */ - DPLL_ID_ICL_MGPLL4 = 5, + DPLL_ID_ICL_MGPLL4 = 6, }; -#define I915_NUM_PLLS 6 +#define I915_NUM_PLLS 7 struct intel_dpll_hw_state { /* i9xx, pch plls */ |