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authorGaurav K Singh <gaurav.k.singh@intel.com>2014-12-10 22:07:40 +0530
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-12-15 09:54:22 +0100
commitf915084edc5aad351d6a4675b0bcdded9a00090d (patch)
tree41721364e029a291f4b9c2e791fe48c7edb2ef01 /drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
parentdrm/i915: Use BUILD_BUG if possible in the i915 WARN_ON (diff)
downloadlinux-dev-f915084edc5aad351d6a4675b0bcdded9a00090d.tar.xz
linux-dev-f915084edc5aad351d6a4675b0bcdded9a00090d.zip
drm/i915: Changes related to the sequence port no for
From now on for both DSI Ports A & C, the seq_port value has been set to 0. seq_port value is parsed from Sequence block#53 of VBT. So, for packets that needs to be read/write for DSI single link on Port A and Port C will now be based on the DVO port from VBT block 2, instead of seq_port. Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to '')
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_panel_vbt.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f8c2269c434c..5493aef5a6a3 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -110,7 +110,15 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
- port = intel_dsi_seq_port_to_port(seq_port);
+ /* For DSI single link on Port A & C, the seq_port value which is
+ * parsed from Sequence Block#53 of VBT has been set to 0
+ * Now, read/write of packets for the DSI single link on Port A and
+ * Port C will based on the DVO port from VBT block 2.
+ */
+ if (intel_dsi->ports == (1 << PORT_C))
+ port = PORT_C;
+ else
+ port = intel_dsi_seq_port_to_port(seq_port);
/* LP or HS mode */
intel_dsi->hs = mode;