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| author |   Damien Lespiau <damien.lespiau@intel.com> | 2015-05-09 02:05:55 +0100 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-05-20 11:25:40 +0200 |
| commit | b6e742f652791919ce5c8e05a1d664bcbc5111a6 (patch) | |
| tree | afe956e9c03877c0dc0dc3a5ac4d146a6e4093e0 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Always keep crtc_state->active in sync with enable (diff) | |
| download | linux-dev-b6e742f652791919ce5c8e05a1d664bcbc5111a6.tar.xz linux-dev-b6e742f652791919ce5c8e05a1d664bcbc5111a6.zip | |
drm/i915: Be optimistic about future display engines having 7 WM levels
As we're doing throughout the code, being optimistic that platform n + 1
will mostly reuse the same things as platform n allows us to minimize
the enabling work needed.
This time, it's about the number of WM levels.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index af2606098cf9..f08264ca1d30 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1946,7 +1946,7 @@ static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) int ilk_wm_max_level(const struct drm_device *dev) { /* how many WM levels are we expecting */ - if (IS_GEN9(dev)) + if (INTEL_INFO(dev)->gen >= 9) return 7; else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) return 4; |