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authorJosé Roberto de Souza <jose.souza@intel.com>2018-12-03 16:34:02 -0800
committerJosé Roberto de Souza <jose.souza@intel.com>2018-12-04 12:12:34 -0800
commitbef5e5b3bee41c6a0706f4a4f66bc9422e6933a1 (patch)
tree771af3dccd585e4792ccf5fe6b87d0f4c73beeef /drivers/gpu/drm/i915/intel_psr.c
parentdrm: Add the PSR SU granularity registers offsets (diff)
downloadlinux-dev-bef5e5b3bee41c6a0706f4a4f66bc9422e6933a1.tar.xz
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drm/i915/psr: Check if resolution is supported by default SU granularity
Selective updates have a default granularity requirements as stated by eDP spec(PSR2 SELECTIVE UPDATE X GRANULARITY CAPABILITY register definition), so check if HW can match those requirements before enabling PSR2. v3: - Changes in the comments and commit message(Dhinakaran) - Printing the hdisplay that do not match with default granularity Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181204003403.23361-8-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_psr.c')
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 11b038ba96ec..298c3145212d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -536,6 +536,17 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
+ /*
+ * HW sends SU blocks of size four scan lines, which means the starting
+ * X coordinate and Y granularity requirements will always be met. We
+ * only need to validate the SU block width is a multiple of 4.
+ */
+ if (crtc_hdisplay % 4) {
+ DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of 4\n",
+ crtc_hdisplay);
+ return false;
+ }
+
return true;
}