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| author |   Ben Skeggs <bskeggs@redhat.com> | 2014-08-10 04:10:26 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-08-10 05:28:07 +1000 |
| commit | bf0eb89859439f016a1fab4cdf737c95f36dbb2e (patch) | |
| tree | 59709bbd702fe904e63a2237d200162f90d820b4 /drivers/gpu/drm/nouveau/nvif/class.h | |
| parent | drm/nv50-/disp: share channel creation between nv50/gf110 impls (diff) | |
| download | linux-dev-bf0eb89859439f016a1fab4cdf737c95f36dbb2e.tar.xz linux-dev-bf0eb89859439f016a1fab4cdf737c95f36dbb2e.zip | |
drm/nv50-/disp: audit and version DAC_PWR method
The full object interfaces are about to be exposed to userspace, so we
need to check for any security-related issues and version the structs
to make it easier to handle any changes we may need in the future.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvif/class.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h index 50c5413ff523..9681a102970d 100644 --- a/drivers/gpu/drm/nouveau/nvif/class.h +++ b/drivers/gpu/drm/nouveau/nvif/class.h @@ -290,4 +290,47 @@ struct kepler_channel_gpfifo_a_v0 { __u64 ioffset; }; +/******************************************************************************* + * legacy display + ******************************************************************************/ + + +/******************************************************************************* + * display + ******************************************************************************/ + +#define NV50_DISP_MTHD 0x00 + +struct nv50_disp_mthd_v0 { + __u8 version; + __u8 method; + __u8 head; + __u8 pad03[5]; +}; + +struct nv50_disp_mthd_v1 { + __u8 version; +#define NV50_DISP_MTHD_V1_DAC_PWR 0x10 +#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 +#define NV50_DISP_MTHD_V1_SOR_PWR 0x20 +#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 +#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 +#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 +#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 +#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 + __u8 method; + __u16 hasht; + __u16 hashm; + __u8 pad06[2]; +}; + +struct nv50_disp_dac_pwr_v0 { + __u8 version; + __u8 state; + __u8 data; + __u8 vsync; + __u8 hsync; + __u8 pad05[3]; +}; + #endif |