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| author |   Chen-Yu Tsai <wens@csie.org> | 2017-10-14 12:02:51 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-10-16 09:54:21 +0200 |
| commit | 31f5232effd30808f96772f123300d9d13f0cfd1 (patch) | |
| tree | 040b5d6a866a90bd472ac3d8fc00b4631c6d9fe7 /drivers/gpu/drm/sun4i/sun4i_hdmi.h | |
| parent | drm/sun4i: backend: Add comment explaining why registers are cleared (diff) | |
| download | linux-dev-31f5232effd30808f96772f123300d9d13f0cfd1.tar.xz linux-dev-31f5232effd30808f96772f123300d9d13f0cfd1.zip | |
drm/sun4i: hdmi: Document PAD_CTRL1 output invert bits
While debugging inverted color from the HDMI output on the A10, I
found that the lowest 3 bits were set. These were cleared on A20
boards that had normal display output. By manually toggling these
bits the mapping of the color components to these bits was found.
While these are not used anywhere, it would be nice to document
them somewhere.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171014040252.9621-7-wens@csie.org
Diffstat (limited to '')
| -rw-r--r-- | drivers/gpu/drm/sun4i/sun4i_hdmi.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h index 9b97da39927e..b685ee11623d 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h @@ -72,6 +72,11 @@ #define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6) #define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n) (((n) & 7) << 3) +/* These bits seem to invert the TMDS data channels */ +#define SUN4I_HDMI_PAD_CTRL1_INVERT_R BIT(2) +#define SUN4I_HDMI_PAD_CTRL1_INVERT_G BIT(1) +#define SUN4I_HDMI_PAD_CTRL1_INVERT_B BIT(0) + #define SUN4I_HDMI_PLL_CTRL_REG 0x208 #define SUN4I_HDMI_PLL_CTRL_PLL_EN BIT(31) #define SUN4I_HDMI_PLL_CTRL_BWS BIT(30) |