diff options
| author |   Yixing Liu <liuyixing1@huawei.com> | 2021-12-07 20:49:01 +0800 |
|---|---|---|
| committer |   Jason Gunthorpe <jgg@nvidia.com> | 2021-12-14 19:59:07 -0400 |
| commit | 0045e0d3f42ed7d05434bb5bc16acfc793ea4891 (patch) | |
| tree | 43beb583ac3757ab6d66cc2d566bc47570a8869d /drivers/infiniband/hw/hns/hns_roce_hw_v2.c | |
| parent | RDMA/qedr: Fix reporting max_{send/recv}_wr attrs (diff) | |
| download | linux-dev-0045e0d3f42ed7d05434bb5bc16acfc793ea4891.tar.xz linux-dev-0045e0d3f42ed7d05434bb5bc16acfc793ea4891.zip | |
RDMA/hns: Support direct wqe of userspace
The current write wqe mechanism is to write to DDR first, and then notify
the hardware through doorbell to read the data. Direct wqe is a mechanism
to fill wqe directly into the hardware. In the case of light load, the wqe
will be filled into pcie bar space of the hardware, this will reduce one
memory access operation and therefore reduce the latency. SIMD
instructions allows cpu to write the 512 bits at one time to device
memory, thus it can be used for posting direct wqe.
Add direct wqe enable switch and address mapping.
Link: https://lore.kernel.org/r/20211207124901.42123-2-liangwenpeng@huawei.com
Signed-off-by: Yixing Liu <liuyixing1@huawei.com>
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index bdf220dc8dd3..2d475348a6cd 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -1989,7 +1989,8 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM; if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) { - caps->flags |= HNS_ROCE_CAP_FLAG_STASH; + caps->flags |= HNS_ROCE_CAP_FLAG_STASH | + HNS_ROCE_CAP_FLAG_DIRECT_WQE; caps->max_sq_inline = HNS_ROCE_V3_MAX_SQ_INLINE; } else { caps->max_sq_inline = HNS_ROCE_V2_MAX_SQ_INLINE; |