diff options
| author |   Wei Hu(Xavier) <xavier.huwei@huawei.com> | 2017-10-18 17:32:46 +0800 |
|---|---|---|
| committer |   Doug Ledford <dledford@redhat.com> | 2017-10-25 13:37:07 -0400 |
| commit | 3180236cceeb3d66e45f6395501f3d315beae4c1 (patch) | |
| tree | 6b41c769eefc136eef1e4891a93dde3603d057e4 /drivers/infiniband/hw/hns/hns_roce_hw_v2.h | |
| parent | RDMA/hns: Update the IRRL table chunk size in hip08 (diff) | |
| download | linux-dev-3180236cceeb3d66e45f6395501f3d315beae4c1.tar.xz linux-dev-3180236cceeb3d66e45f6395501f3d315beae4c1.zip | |
RDMA/hns: Update the PD&CQE&MTT specification in hip08
This patch updates the PD specification to 16M for hip08. And it
updates the numbers of mtt and cqe segments for the buddy.
As the CQE supports hop num 1 addressing, the CQE specification is
64k. This patch updates to set the CQE specification to 64k.
Signed-off-by: Shaobo Xu <xushaobo2@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index 65ed3f861f54..6106ad1b1322 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -47,16 +47,16 @@ #define HNS_ROCE_V2_MAX_QP_NUM 0x2000 #define HNS_ROCE_V2_MAX_WQE_NUM 0x8000 #define HNS_ROCE_V2_MAX_CQ_NUM 0x8000 -#define HNS_ROCE_V2_MAX_CQE_NUM 0x400000 +#define HNS_ROCE_V2_MAX_CQE_NUM 0x10000 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM 0x100 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM 0xff #define HNS_ROCE_V2_MAX_SQ_INLINE 0x20 #define HNS_ROCE_V2_UAR_NUM 256 #define HNS_ROCE_V2_PHY_UAR_NUM 1 #define HNS_ROCE_V2_MAX_MTPT_NUM 0x8000 -#define HNS_ROCE_V2_MAX_MTT_SEGS 0x100000 -#define HNS_ROCE_V2_MAX_CQE_SEGS 0x10000 -#define HNS_ROCE_V2_MAX_PD_NUM 0x400000 +#define HNS_ROCE_V2_MAX_MTT_SEGS 0x1000000 +#define HNS_ROCE_V2_MAX_CQE_SEGS 0x1000000 +#define HNS_ROCE_V2_MAX_PD_NUM 0x1000000 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA 128 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA 128 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ 64 |