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| author |   oulijun <oulijun@huawei.com> | 2018-07-09 17:48:10 +0800 |
|---|---|---|
| committer |   Jason Gunthorpe <jgg@mellanox.com> | 2018-07-11 14:09:25 -0600 |
| commit | e8e8b65224625f7d4dc7953484afe1b571db6c73 (patch) | |
| tree | 7df88d88958e412c9c50e91bb5f7d4299f734595 /drivers/infiniband/hw/hns/hns_roce_hw_v2.h | |
| parent | RDMA/hns: Update the implementation of set_gid (diff) | |
| download | linux-dev-e8e8b65224625f7d4dc7953484afe1b571db6c73.tar.xz linux-dev-e8e8b65224625f7d4dc7953484afe1b571db6c73.zip | |
RDMA/hns: Update the implementation of set_mac
This patch updates the implementation of set_mac by using
command queue instead of directly writing registers.
Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Yixian Liu <liuyixian@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
Diffstat (limited to '')
| -rw-r--r-- | drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index 169f747b2d7c..df95b3515c94 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -206,6 +206,7 @@ enum hns_roce_opcode_type { HNS_ROCE_OPC_CFG_EXT_LLM = 0x8403, HNS_ROCE_OPC_CFG_TMOUT_LLM = 0x8404, HNS_ROCE_OPC_CFG_SGID_TB = 0x8500, + HNS_ROCE_OPC_CFG_SMAC_TB = 0x8501, HNS_ROCE_OPC_CFG_BT_ATTR = 0x8506, }; @@ -1242,10 +1243,6 @@ struct hns_roce_vf_res_b { #define VF_RES_B_DATA_3_VF_SL_NUM_S 16 #define VF_RES_B_DATA_3_VF_SL_NUM_M GENMASK(19, 16) -/* Reg field definition */ -#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_S 0 -#define ROCEE_VF_SMAC_CFG1_VF_SMAC_H_M GENMASK(15, 0) - struct hns_roce_cfg_bt_attr { __le32 vf_qpc_cfg; __le32 vf_srqc_cfg; @@ -1304,6 +1301,18 @@ struct hns_roce_cfg_sgid_tb { #define CFG_SGID_TB_VF_SGID_TYPE_S 0 #define CFG_SGID_TB_VF_SGID_TYPE_M GENMASK(1, 0) +struct hns_roce_cfg_smac_tb { + __le32 tb_idx_rsv; + __le32 vf_smac_l; + __le32 vf_smac_h_rsv; + __le32 rsv[3]; +}; +#define CFG_SMAC_TB_IDX_S 0 +#define CFG_SMAC_TB_IDX_M GENMASK(7, 0) + +#define CFG_SMAC_TB_VF_SMAC_H_S 0 +#define CFG_SMAC_TB_VF_SMAC_H_M GENMASK(15, 0) + struct hns_roce_cmq_desc { __le16 opcode; __le16 flag; |