aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/infiniband/ulp/rtrs/rtrs.c
diff options
context:
space:
mode:
authorJack Wang <jinpu.wang@ionos.com>2021-07-12 08:07:47 +0200
committerJason Gunthorpe <jgg@nvidia.com>2021-07-15 14:24:14 -0300
commite2d98504c697f9c8e45b815062f8893b10808d8e (patch)
treecf1e8f39bcf296a8fb316fac7921bb40d6459aec /drivers/infiniband/ulp/rtrs/rtrs.c
parentRDMA/rtrs: move wr_cnt from rtrs_srv_con to rtrs_con (diff)
downloadlinux-dev-e2d98504c697f9c8e45b815062f8893b10808d8e.tar.xz
linux-dev-e2d98504c697f9c8e45b815062f8893b10808d8e.zip
RDMA/rtrs: Enable the same selective signal for heartbeat and IO
On idle session, because we do not do signal for heartbeat, it will overflow the send queue after sometime. To avoid that, we need to enable the signal for heartbeat. To do that, add a new member signal_interval in rtrs_path, which will set min of queue_depth and SERVICE_CON_QUEUE_DEPTH, and track it for both heartbeat and IO, so the sq queue full accounting is correct. Fixes: b38041d50add ("RDMA/rtrs: Do not signal for heatbeat") Link: https://lore.kernel.org/r/20210712060750.16494-4-jinpu.wang@ionos.com Signed-off-by: Jack Wang <jinpu.wang@ionos.com> Reviewed-by: Aleksei Marov <aleksei.marov@ionos.com> Reviewed-by: Gioh Kim <gi-oh.kim@ionos.com> Reviewed-by: Md Haris Iqbal <haris.iqbal@ionos.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to '')
-rw-r--r--drivers/infiniband/ulp/rtrs/rtrs.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/infiniband/ulp/rtrs/rtrs.c b/drivers/infiniband/ulp/rtrs/rtrs.c
index 870b21f551a4..7f2dfb9d11fc 100644
--- a/drivers/infiniband/ulp/rtrs/rtrs.c
+++ b/drivers/infiniband/ulp/rtrs/rtrs.c
@@ -187,10 +187,15 @@ int rtrs_post_rdma_write_imm_empty(struct rtrs_con *con, struct ib_cqe *cqe,
struct ib_send_wr *head)
{
struct ib_rdma_wr wr;
+ struct rtrs_sess *sess = con->sess;
+ enum ib_send_flags sflags;
+
+ sflags = (atomic_inc_return(&con->wr_cnt) % sess->signal_interval) ?
+ 0 : IB_SEND_SIGNALED;
wr = (struct ib_rdma_wr) {
.wr.wr_cqe = cqe,
- .wr.send_flags = flags,
+ .wr.send_flags = sflags,
.wr.opcode = IB_WR_RDMA_WRITE_WITH_IMM,
.wr.ex.imm_data = cpu_to_be32(imm_data),
};