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author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2019-05-10 11:43:46 -0700 |
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committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2019-05-10 11:43:46 -0700 |
commit | 2a267e7c41aa88215de2b542de797d03d16ecdfd (patch) | |
tree | b949270835e304c8b60a40cde1b2c2e19c13b33a /drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h | |
parent | Input: libps2 - mark expected switch fall-through (diff) | |
parent | Linux 5.1 (diff) | |
download | linux-dev-2a267e7c41aa88215de2b542de797d03d16ecdfd.tar.xz linux-dev-2a267e7c41aa88215de2b542de797d03d16ecdfd.zip |
Merge tag 'v5.1' into next
Sync up with mainline to bring in the latest APIs.
Diffstat (limited to 'drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h')
-rw-r--r-- | drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h new file mode 100644 index 000000000000..f23cb3e41c30 --- /dev/null +++ b/drivers/misc/habanalabs/include/goya/asic_reg/cpu_if_regs.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2018 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_CPU_IF_REGS_H_ +#define ASIC_REG_CPU_IF_REGS_H_ + +/* + ***************************************** + * CPU_IF (Prototype: CPU_IF) + ***************************************** + */ + +#define mmCPU_IF_PF_PQ_PI 0x442100 + +#define mmCPU_IF_ARUSER_OVR 0x442104 + +#define mmCPU_IF_ARUSER_OVR_EN 0x442108 + +#define mmCPU_IF_AWUSER_OVR 0x44210C + +#define mmCPU_IF_AWUSER_OVR_EN 0x442110 + +#define mmCPU_IF_AXCACHE_OVR 0x442114 + +#define mmCPU_IF_LOCK_OVR 0x442118 + +#define mmCPU_IF_PROT_OVR 0x44211C + +#define mmCPU_IF_MAX_OUTSTANDING 0x442120 + +#define mmCPU_IF_EARLY_BRESP_EN 0x442124 + +#define mmCPU_IF_FORCE_RSP_OK 0x442128 + +#define mmCPU_IF_CPU_MSB_ADDR 0x44212C + +#define mmCPU_IF_AXI_SPLIT_INTR 0x442130 + +#endif /* ASIC_REG_CPU_IF_REGS_H_ */ + |