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authorGuennadi Liakhovetski <g.liakhovetski@gmx.de>2012-12-12 15:38:17 +0100
committerChris Ball <cjb@laptop.org>2013-02-11 13:28:38 -0500
commit276bc96b2abfa2a6bb219aa4eda13c4c331c53eb (patch)
tree4edc707d40597d431acfe8dd99ae1f9d62a78574 /drivers/mmc/host/sh_mmcif.c
parentmmc: sh_mmcif: reset DMA completion immediately before starting DMA (diff)
downloadlinux-dev-276bc96b2abfa2a6bb219aa4eda13c4c331c53eb.tar.xz
linux-dev-276bc96b2abfa2a6bb219aa4eda13c4c331c53eb.zip
mmc: sh_mmcif: fix I/O errors
The INT_BUFWEN IRQ often arrives with other bits set too. If they are not cleared, an additional IRQ can be triggered, sometimes also after the MMC request has already been completed. This leads to block I/O errors. Earlier Teppei Kamijou also observed these additional interrupts and proposed to explicitly wait for them. This patch chooses an alternative approach of clearing all active bits immediately, when processing the main interrupt. Reported-by: Teppei Kamijou <teppei.kamijou.yb@renesas.com> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to '')
-rw-r--r--drivers/mmc/host/sh_mmcif.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index 1c37854c0f33..e6a6d2363a4d 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -1238,7 +1238,9 @@ static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
} else if (state & INT_BUFWEN) {
- sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
+ sh_mmcif_writel(host->addr, MMCIF_CE_INT,
+ ~(INT_BUFWEN | INT_DTRANE | INT_CMD12DRE |
+ INT_CMD12RBE | INT_CMD12CRE));
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
} else if (state & INT_CMD12DRE) {
sh_mmcif_writel(host->addr, MMCIF_CE_INT,