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| author |   Paulius Zaleckas <paulius.zaleckas@gmail.com> | 2010-04-23 13:17:47 -0400 |
|---|---|---|
| committer |   Linus Torvalds <torvalds@linux-foundation.org> | 2010-04-24 11:31:24 -0700 |
| commit | a88a2b886404b1cfc109125b1cba4775e8682955 (patch) | |
| tree | dda4d73b5eb041c728bd970d574ed211208b5a5a /drivers/mtd/nand/orion_nand.c | |
| parent | flex_array: fix the panic when calling flex_array_alloc() without __GFP_ZERO (diff) | |
| download | linux-dev-a88a2b886404b1cfc109125b1cba4775e8682955.tar.xz linux-dev-a88a2b886404b1cfc109125b1cba4775e8682955.zip | |
mtd: fix Orion NAND driver compilation with ARM OABI
We must tell GCC to use even register for variable passed to ldrd
instruction. Without this patch GCC 4.2.1 puts this variable to r2/r3 on
EABI and r3/r4 on OABI, so force it to r2/r3. This does not change
anything when EABI and OABI compilation works OK.
Without this patch and with OABI I get:
CC drivers/mtd/nand/orion_nand.o
/tmp/ccMkwOCs.s: Assembler messages:
/tmp/ccMkwOCs.s:63: Error: first destination register must be even -- `ldrd r3,[ip]'
make[5]: *** [drivers/mtd/nand/orion_nand.o] Error 1
Signed-off-by: Paulius Zaleckas <paulius.zaleckas@gmail.com>
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Acked-by: Artem Bityutskiy <dedekind1@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Jamie Lokier <jamie@shareable.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to '')
| -rw-r--r-- | drivers/mtd/nand/orion_nand.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c index f59c07427af3..d60fc5719fef 100644 --- a/drivers/mtd/nand/orion_nand.c +++ b/drivers/mtd/nand/orion_nand.c @@ -60,7 +60,13 @@ static void orion_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) } buf64 = (uint64_t *)buf; while (i < len/8) { - uint64_t x; + /* + * Since GCC has no proper constraint (PR 43518) + * force x variable to r2/r3 registers as ldrd instruction + * requires first register to be even. + */ + register uint64_t x asm ("r2"); + asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base)); buf64[i++] = x; } |