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| author |   Yaniv Rosner <yanivr@broadcom.com> | 2011-05-31 21:28:10 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2011-06-01 13:10:56 -0700 |
| commit | bac27bd941454aaf40f7876ce3b487e303c4953d (patch) | |
| tree | 40579b326cb0bee86603a7b76db4e6b4dfbcde00 /drivers/net/bnx2x/bnx2x_reg.h | |
| parent | bnx2x: Fix over current port display (diff) | |
| download | linux-dev-bac27bd941454aaf40f7876ce3b487e303c4953d.tar.xz linux-dev-bac27bd941454aaf40f7876ce3b487e303c4953d.zip | |
bnx2x: Fix BCM84833 settings
Fix BCM84833 register settings.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/bnx2x/bnx2x_reg.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h index 7260d09cf25f..11d35250b092 100644 --- a/drivers/net/bnx2x/bnx2x_reg.h +++ b/drivers/net/bnx2x/bnx2x_reg.h @@ -6202,6 +6202,29 @@ Theotherbitsarereservedandshouldbezero*/ #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 +/* BCM84833 only */ +#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a +#define MDIO_84833_SUPER_ISOLATE 0x8000 +/* These are mailbox register set used by 84833. */ +#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 +#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 +#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 +#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 +#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 + +/* Mailbox command set used by 84833. */ +#define PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE 0x2 +/* Mailbox status set used by 84833. */ +#define PHY84833_CMD_RECEIVED 0x0001 +#define PHY84833_CMD_IN_PROGRESS 0x0002 +#define PHY84833_CMD_COMPLETE_PASS 0x0004 +#define PHY84833_CMD_COMPLETE_ERROR 0x0008 +#define PHY84833_CMD_OPEN_FOR_CMDS 0x0010 +#define PHY84833_CMD_SYSTEM_BOOT 0x0020 +#define PHY84833_CMD_NOT_OPEN_FOR_CMDS 0x0040 +#define PHY84833_CMD_CLEAR_COMPLETE 0x0080 +#define PHY84833_CMD_OPEN_OVERRIDE 0xa5a5 + #define IGU_FUNC_BASE 0x0400 #define IGU_ADDR_MSIX 0x0000 |