diff options
| author |   Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> | 2020-04-20 15:26:54 +0530 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2020-04-20 12:54:30 -0700 |
| commit | bd019427bf3623ee3c7d2845cf921bbf4c14846c (patch) | |
| tree | 00b718553509b066a30df2f14cd310d317866c60 /drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | |
| parent | net: stmmac: dwmac-meson8b: Add missing boundary to RGMII TX clock array (diff) | |
| download | linux-dev-bd019427bf3623ee3c7d2845cf921bbf4c14846c.tar.xz linux-dev-bd019427bf3623ee3c7d2845cf921bbf4c14846c.zip | |
cxgb4: fix large delays in PTP synchronization
Fetching PTP sync information from mailbox is slow and can take
up to 10 milliseconds. Reduce this unnecessary delay by directly
reading the information from the corresponding registers.
Fixes: 9c33e4208bce ("cxgb4: Add PTP Hardware Clock (PHC) support")
Signed-off-by: Manoj Malviya <manojmalviya@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h index bb20e50ddb84..4a9fcd6c226c 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h @@ -1906,6 +1906,9 @@ #define MAC_PORT_CFG2_A 0x818 +#define MAC_PORT_PTP_SUM_LO_A 0x990 +#define MAC_PORT_PTP_SUM_HI_A 0x994 + #define MPS_CMN_CTL_A 0x9000 #define COUNTPAUSEMCRX_S 5 |