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authorClaudiu Manoil <claudiu.manoil@freescale.com>2013-08-12 13:53:26 +0300
committerDavid S. Miller <davem@davemloft.net>2013-08-13 15:28:53 -0700
commit23402bddf9e56eecb27bbd1e5467b3b79b3dbe58 (patch)
tree26dc3784f50481c3ac8457abccd54bd7aec1748a /drivers/net/ethernet/freescale/gianfar.h
parentpptp: fix byte order warnings (diff)
downloadlinux-dev-23402bddf9e56eecb27bbd1e5467b3b79b3dbe58.tar.xz
linux-dev-23402bddf9e56eecb27bbd1e5467b3b79b3dbe58.zip
gianfar: Add flow control support
eTSEC has Rx and Tx flow control capabilities that may be enabled through MACCFG1[Rx_Flow, Tx_Flow] bits. These bits must not be set however when eTSEC is operated in Half-Duplex mode. Unfortunately, the driver currently sets these bits unconditionally. This patch adds the proper handling of the PAUSE frame capability register bits by implementing the ethtool -A interface. When pause autoneg is enabled, the controller uses the phy's capability to negotiate PAUSE frame settings with the link partner and reconfigures its Rx_Flow and Tx_Flow settings to match the capabilities of the link partner. If pause autoneg is off, the PAUSE frame generation may be forced manually (ethtool -A). Flow control is disabled by default now. This implementation is inspired by the tg3 driver. Signed-off-by: Lutz Jaenicke <ljaenicke@innominate.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/freescale/gianfar.h')
-rw-r--r--drivers/net/ethernet/freescale/gianfar.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/net/ethernet/freescale/gianfar.h b/drivers/net/ethernet/freescale/gianfar.h
index ee19f2c138a6..46f56f36118f 100644
--- a/drivers/net/ethernet/freescale/gianfar.h
+++ b/drivers/net/ethernet/freescale/gianfar.h
@@ -146,6 +146,10 @@ extern const char gfar_driver_version[];
| SUPPORTED_Autoneg \
| SUPPORTED_MII)
+#define GFAR_SUPPORTED_GBIT (SUPPORTED_1000baseT_Full \
+ | SUPPORTED_Pause \
+ | SUPPORTED_Asym_Pause)
+
/* TBI register addresses */
#define MII_TBICON 0x11
@@ -1100,7 +1104,11 @@ struct gfar_private {
/* Wake-on-LAN enabled */
wol_en:1,
/* Enable priorty based Tx scheduling in Hw */
- prio_sched_en:1;
+ prio_sched_en:1,
+ /* Flow control flags */
+ pause_aneg_en:1,
+ tx_pause_en:1,
+ rx_pause_en:1;
/* The total tx and rx ring size for the enabled queues */
unsigned int total_tx_ring_size;