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| author |   Weihang Li <liweihang@hisilicon.com> | 2019-04-14 09:47:43 +0800 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2019-04-14 13:47:35 -0700 |
| commit | c41e672d1e6a51b2b21a23ade4048b414ec76624 (patch) | |
| tree | 8b94e4ef0a4d8d6e6c215c4d772df615d78a3b42 /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | |
| parent | net: hns3: divide shared buffer between TC (diff) | |
| download | linux-dev-c41e672d1e6a51b2b21a23ade4048b414ec76624.tar.xz linux-dev-c41e672d1e6a51b2b21a23ade4048b414ec76624.zip | |
net: hns3: set dividual reset level for all RAS and MSI-X errors
According to hardware description, reset level that should be
triggered are not consistent in a module. For example, in SSU
common errors, the first two bits has no need to do reset,
but the other bits need global reset.
This patch sets separate reset level for all RAS and MSI-X
interrupts by adding a reset_lvel field in struct hclge_hw_error,
and fixes some incorrect reset level.
Signed-off-by: Weihang Li <liweihang@hisilicon.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h index fc068280d391..4a2e82f7f112 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h @@ -112,6 +112,7 @@ struct hclge_hw_blk { struct hclge_hw_error { u32 int_msk; const char *msg; + enum hnae3_reset_type reset_level; }; int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state); |