diff options
| author |   Shiju Jose <shiju.jose@huawei.com> | 2018-10-19 20:15:31 +0100 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2018-10-22 19:31:14 -0700 |
| commit | da2d072a9ea75dd5babebcfd71144fb5b3aa9913 (patch) | |
| tree | f70df477c4e8e48d4ae1c4af1a8e756e2cb85eb4 /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | |
| parent | net: hns3: Add enable and process hw errors from IGU, EGU and NCSI (diff) | |
| download | linux-dev-da2d072a9ea75dd5babebcfd71144fb5b3aa9913.tar.xz linux-dev-da2d072a9ea75dd5babebcfd71144fb5b3aa9913.zip | |
net: hns3: Add enable and process hw errors from PPP
This patch enables and process hw errors from the
PPP(Programmable Packet Process) block.
Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h index f46c8c29a17e..c6d373929be6 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h @@ -27,6 +27,16 @@ #define HCLGE_IGU_ERR_INT_EN_MASK 0x000F #define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF #define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F +#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF +#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF +#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF +#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF +#define HCLGE_PPP_PF_ERR_INT_EN 0x0003 +#define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003 +#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F +#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F +#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F +#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F #define HCLGE_NCSI_ERR_INT_EN 0x3 #define HCLGE_NCSI_ERR_INT_TYPE 0x9 @@ -43,6 +53,7 @@ #define HCLGE_TQP_IMP_ERR_CLR_MASK 0x0FFF0001 #define HCLGE_IGU_COM_INT_MASK 0xF #define HCLGE_IGU_EGU_TNL_INT_MASK 0x3F +#define HCLGE_PPP_PF_INT_MASK 0x100 enum hclge_err_int_type { HCLGE_ERR_INT_MSIX = 0, |