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| author |   Salil Mehta <salil.mehta@huawei.com> | 2017-11-13 11:39:38 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2017-11-14 21:46:00 +0900 |
| commit | 887c3820a3801a117a494aeca147ec52f95e1566 (patch) | |
| tree | 9cb6996a66916f0727d6ba8c0bfb52190c2a2e32 /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | |
| parent | net: dsa: lan9303: correctly check return value of devm_gpiod_get_optional (diff) | |
| download | linux-dev-887c3820a3801a117a494aeca147ec52f95e1566.tar.xz linux-dev-887c3820a3801a117a494aeca147ec52f95e1566.zip | |
net: hns3: Updates MSI/MSI-X alloc/free APIs(depricated) to new APIs
This patch migrates the HNS3 driver code from use of depricated PCI
MSI/MSI-X interrupt vector allocation/free APIs to new common APIs.
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Suggested-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index 742e6ee9efaf..7027814ea5d7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -425,9 +425,6 @@ struct hclge_dev { u16 num_tqps; /* Num task queue pairs of this PF */ u16 num_req_vfs; /* Num VFs requested for this PF */ - u16 num_roce_msix; /* Num of roce vectors for this PF */ - int roce_base_vector; - /* Base task tqp physical id of this PF */ u16 base_tqp_pid; u16 alloc_rss_size; /* Allocated RSS task queue */ @@ -457,8 +454,10 @@ struct hclge_dev { u16 num_msi_left; u16 num_msi_used; u32 base_msi_vector; - struct msix_entry *msix_entries; u16 *vector_status; + int *vector_irq; + u16 num_roce_msi; /* Num of roce vectors for this PF */ + int roce_base_vector; u16 pending_udp_bitmap; @@ -482,12 +481,10 @@ struct hclge_dev { struct hnae3_client *nic_client; struct hnae3_client *roce_client; -#define HCLGE_FLAG_USE_MSI 0x00000001 -#define HCLGE_FLAG_USE_MSIX 0x00000002 -#define HCLGE_FLAG_MAIN 0x00000004 -#define HCLGE_FLAG_DCB_CAPABLE 0x00000008 -#define HCLGE_FLAG_DCB_ENABLE 0x00000010 -#define HCLGE_FLAG_MQPRIO_ENABLE 0x00000020 +#define HCLGE_FLAG_MAIN BIT(0) +#define HCLGE_FLAG_DCB_CAPABLE BIT(1) +#define HCLGE_FLAG_DCB_ENABLE BIT(2) +#define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) u32 flag; u32 pkt_buf_size; /* Total pf buf size for tx/rx */ |