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| author |   Huazhong Tan <tanhuazhong@huawei.com> | 2019-08-28 22:23:15 +0800 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2019-08-29 16:57:44 -0700 |
| commit | 2336f19d789223b9f42f111aab8de6ad66d12c28 (patch) | |
| tree | 45ea9966d56dc8b260b5483ca5b02eb10a3fba54 /drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | |
| parent | net: hns3: add phy selftest function (diff) | |
| download | linux-dev-2336f19d789223b9f42f111aab8de6ad66d12c28.tar.xz linux-dev-2336f19d789223b9f42f111aab8de6ad66d12c28.zip | |
net: hns3: check reset interrupt status when reset fails
Currently, the reset interrupt will be cleared firstly, so when
reset fails, if interrupt status register has reset interrupt,
it means there is a new coming reset.
Fixes: 72e2fb07997c ("net: hns3: clear reset interrupt status in hclge_irq_handle()")
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Reviewed-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index a3bc382926bb..437a9ff8f588 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -164,6 +164,7 @@ enum HLCGE_PORT_TYPE { #define HCLGE_GLOBAL_RESET_BIT 0 #define HCLGE_CORE_RESET_BIT 1 #define HCLGE_IMP_RESET_BIT 2 +#define HCLGE_RESET_INT_M GENMASK(2, 0) #define HCLGE_FUN_RST_ING 0x20C00 #define HCLGE_FUN_RST_ING_B 0 |