diff options
| author |   Huazhong Tan <tanhuazhong@huawei.com> | 2018-11-09 22:07:49 +0800 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2018-11-09 16:47:34 -0800 |
| commit | b90fcc5bd904fe1ec1b4b0a5ba8299cd2625a16c (patch) | |
| tree | 98cb2aa709362aa16ef518b716938b86bfec04c1 /drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | |
| parent | net: hns3: add reset handling for VF when doing PF reset (diff) | |
| download | linux-dev-b90fcc5bd904fe1ec1b4b0a5ba8299cd2625a16c.tar.xz linux-dev-b90fcc5bd904fe1ec1b4b0a5ba8299cd2625a16c.zip | |
net: hns3: add reset handling for VF when doing Core/Global/IMP reset
When a Core/Global/IMP reset occurs, the hardware sets the reset status
register of all PF/VF and reports a reset interrupt to all PF/VF and
firmware.
When receiving the reset interrupt:
1. The firmware will wait for 100 ms before resetting the hardware and
clear the reset status register of all PF when hardware reset is done.
2. The PF/VF driver needs to down the netdev within 100 ms and then wait
for hardware reset to finish.
3. After firmware clearing the reset status register of all PF, the PF
driver reinitializes the hardware and clear the reset status register
of it's VF.
4. After PF driver clearing the reset status register of VF, the VF driver
reinitializes the hardware.
This patch mainly add handling for the step 4.
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h index 2735414cc9ce..e37897df6afc 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h @@ -31,6 +31,8 @@ #define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100 /* CMDQ register bits for RX event(=MBX event) */ #define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1 +/* RST register bits for RESET event */ +#define HCLGEVF_VECTOR0_RST_INT_B 2 #define HCLGEVF_TQP_RESET_TRY_TIMES 10 /* Reset related Registers */ @@ -60,6 +62,12 @@ #define HCLGEVF_S_IP_BIT BIT(3) #define HCLGEVF_V_TAG_BIT BIT(4) +enum hclgevf_evt_cause { + HCLGEVF_VECTOR0_EVENT_RST, + HCLGEVF_VECTOR0_EVENT_MBX, + HCLGEVF_VECTOR0_EVENT_OTHER, +}; + /* states of hclgevf device & tasks */ enum hclgevf_states { /* device states */ |