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| author |   Stefan Chulski <stefanc@marvell.com> | 2020-11-23 19:54:33 +0200 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2020-11-24 15:05:04 -0800 |
| commit | 9a71baf719968576326c6a6bc0a57af0e6413c50 (patch) | |
| tree | 8e3e1417c7b0ece1c29d72b8333d9f16a93ded49 /drivers/net/ethernet/marvell/mvneta.c | |
| parent | net: page_pool: Add page_pool_put_page_bulk() to page_pool.rst (diff) | |
| download | linux-dev-9a71baf719968576326c6a6bc0a57af0e6413c50.tar.xz linux-dev-9a71baf719968576326c6a6bc0a57af0e6413c50.zip | |
net: mvpp2: divide fifo for dts-active ports only
Tx/Rx FIFO is a HW resource limited by total size, but shared
by all ports of same CP110 and impacting port-performance.
Do not divide the FIFO for ports which are not enabled in DTS,
so active ports could have more FIFO.
No change in FIFO allocation if all 3 ports on the communication
processor enabled in DTS.
The active port mapping should be done in probe before FIFO-init.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
Link: https://lore.kernel.org/r/1606154073-28267-1-git-send-email-stefanc@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions