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authorRussell King <rmk+kernel@armlinux.org.uk>2019-02-09 16:06:51 +0000
committerDavid S. Miller <davem@davemloft.net>2019-02-09 09:34:00 -0800
commite240b7dbb73c4d5a2997356992a3cfe3ff99951a (patch)
treecf3c01ba1e908e1034c4d1cf92d9c4f351fb314a /drivers/net/ethernet/marvell/mvpp2
parentnet: phy: Add support for asking the PHY its abilities (diff)
downloadlinux-dev-e240b7dbb73c4d5a2997356992a3cfe3ff99951a.tar.xz
linux-dev-e240b7dbb73c4d5a2997356992a3cfe3ff99951a.zip
net: marvell: mvpp2: clear flow control modes in 10G mode
When mvpp2 configures the flow control modes in mvpp2_xlg_config() for 10G mode, it only ever set the flow control enable bits. There is no mechanism to clear these bits, which means that userspace is unable to use standard APIs to disable flow control (the only way is to poke the register directly.) Fix the missing bit clearance to allow flow control to be disabled. This means that, by default, as there is no negotiation in 10G modes with mvpp2, flow control is now disabled rather than being rx-only. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/mvpp2')
-rw-r--r--drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 8a2dd9104e37..eef8833e5aae 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -4515,8 +4515,13 @@ static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
if (state->pause & MLO_PAUSE_TX)
ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
+ else
+ ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
+
if (state->pause & MLO_PAUSE_RX)
ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
+ else
+ ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC |