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authorJiri Pirko <jiri@mellanox.com>2017-06-06 14:12:04 +0200
committerDavid S. Miller <davem@davemloft.net>2017-06-06 12:45:23 -0400
commitbe8408e1440cbc86683e4e1c65270ad517b4274a (patch)
treec18da9da37f5abda6d8e1d5ef52e21fb6a21a16e /drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
parentnet: sched: introduce helper to identify gact trap action (diff)
downloadlinux-dev-be8408e1440cbc86683e4e1c65270ad517b4274a.tar.xz
linux-dev-be8408e1440cbc86683e4e1c65270ad517b4274a.zip
mlxsw: pci: Fix size of trap_id field in CQE
The "trap_id" is 9bits long. So far, this was not a problem since we used only traps with ids that fit into 8bits. But the ACL traps that are going to be introduced use the 9th bit. Fixes: eda6500a987a ("mlxsw: Add PCI bus implementation") Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Yotam Gigi <yotamg@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/pci_hw.h')
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/pci_hw.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
index 0af3338bfcb4..a6441208e9d9 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
@@ -155,7 +155,7 @@ MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
/* pci_cqe_trap_id
* Trap ID that captured the packet.
*/
-MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 8);
+MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
/* pci_cqe_crc
* Length include CRC. Indicates the length field includes