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authorHeiner Kallweit <hkallweit1@gmail.com>2019-06-10 18:21:50 +0200
committerDavid S. Miller <davem@davemloft.net>2019-06-10 10:37:34 -0700
commitec9a40881732c834fe7ffe224981a35043e6a725 (patch)
treefecce9a4817b9fc67b8c8b23c0e0c988535e5f82 /drivers/net/ethernet/realtek
parentcxgb4/libcxgb/cxgb4i/cxgbit: enable eDRAM page pods for iSCSI (diff)
downloadlinux-dev-ec9a40881732c834fe7ffe224981a35043e6a725.tar.xz
linux-dev-ec9a40881732c834fe7ffe224981a35043e6a725.zip
r8169: improve setting interrupt mask
So far several places in the code deal with setting the interrupt mask for the respective chip versions. Improve this by having one function for this only. In addition don't set RxFIFOOver for all 8101 chip versions like in the vendor driver. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/realtek')
-rw-r--r--drivers/net/ethernet/realtek/r8169_main.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
index 8b7d45ff1d03..c62e6845fe9b 100644
--- a/drivers/net/ethernet/realtek/r8169_main.c
+++ b/drivers/net/ethernet/realtek/r8169_main.c
@@ -5136,20 +5136,11 @@ static void rtl_hw_start_8168(struct rtl8169_private *tp)
{
RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
- /* Workaround for RxFIFO overflow. */
- if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
- tp->irq_mask |= RxFIFOOver;
- tp->irq_mask &= ~RxOverflow;
- }
-
rtl_hw_config(tp);
}
static void rtl_hw_start_8101(struct rtl8169_private *tp)
{
- if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
- tp->irq_mask &= ~RxFIFOOver;
-
if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
tp->mac_version == RTL_GIGA_MAC_VER_16)
pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
@@ -6491,29 +6482,38 @@ static const struct net_device_ops rtl_netdev_ops = {
static const struct rtl_cfg_info {
void (*hw_start)(struct rtl8169_private *tp);
- u16 irq_mask;
unsigned int has_gmii:1;
const struct rtl_coalesce_info *coalesce_info;
} rtl_cfg_infos [] = {
[RTL_CFG_0] = {
.hw_start = rtl_hw_start_8169,
- .irq_mask = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
.has_gmii = 1,
.coalesce_info = rtl_coalesce_info_8169,
},
[RTL_CFG_1] = {
.hw_start = rtl_hw_start_8168,
- .irq_mask = LinkChg | RxOverflow,
.has_gmii = 1,
.coalesce_info = rtl_coalesce_info_8168_8136,
},
[RTL_CFG_2] = {
.hw_start = rtl_hw_start_8101,
- .irq_mask = LinkChg | RxOverflow | RxFIFOOver,
.coalesce_info = rtl_coalesce_info_8168_8136,
}
};
+static void rtl_set_irq_mask(struct rtl8169_private *tp)
+{
+ tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
+
+ if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
+ tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
+ else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
+ /* special workaround needed */
+ tp->irq_mask |= RxFIFOOver;
+ else
+ tp->irq_mask |= RxOverflow;
+}
+
static int rtl_alloc_irq(struct rtl8169_private *tp)
{
unsigned int flags;
@@ -6874,8 +6874,8 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
jumbo_max = rtl_jumbo_max(tp);
dev->max_mtu = jumbo_max;
+ rtl_set_irq_mask(tp);
tp->hw_start = cfg->hw_start;
- tp->irq_mask = RTL_EVENT_NAPI | cfg->irq_mask;
tp->coalesce_info = cfg->coalesce_info;
tp->fw_name = rtl_chip_infos[chipset].fw_name;