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| author |   Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-06-26 18:42:33 +0300 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2018-06-28 16:02:04 +0900 |
| commit | 782e85c5f7aee0294cefb52a190b05e082c178d5 (patch) | |
| tree | 401a187ebb0f12d342af085d5a563dd0fd8fb838 /drivers/net/ethernet/renesas/sh_eth.h | |
| parent | tc-tests: add an extreme-case csum action test (diff) | |
| download | linux-dev-782e85c5f7aee0294cefb52a190b05e082c178d5.tar.xz linux-dev-782e85c5f7aee0294cefb52a190b05e082c178d5.zip | |
sh_eth: fix *enum* {A|M}PR_BIT
The *enum* {A|M}PR_BIT were declared in the commit 86a74ff21a7a ("net:
sh_eth: add support for Renesas SuperH Ethernet") adding SH771x support,
however the SH771x manual doesn't have the APR/MPR registers described
and the code writing to them for SH7710 was later removed by the commit
380af9e390ec ("net: sh_eth: CPU dependency code collect to "struct
sh_eth_cpu_data""). All the newer SoC manuals have these registers
documented as having a 16-bit TIME parameter of the PAUSE frame, not
1-bit -- update the *enum* accordingly, fixing up the APR/MPR writes...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/ethernet/renesas/sh_eth.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/renesas/sh_eth.h b/drivers/net/ethernet/renesas/sh_eth.h index a03d99f51ccf..140ad2c57095 100644 --- a/drivers/net/ethernet/renesas/sh_eth.h +++ b/drivers/net/ethernet/renesas/sh_eth.h @@ -383,12 +383,12 @@ enum ECSIPR_STATUS_MASK_BIT { /* APR */ enum APR_BIT { - APR_AP = 0x00000001, + APR_AP = 0x0000ffff, }; /* MPR */ enum MPR_BIT { - MPR_MP = 0x00000001, + MPR_MP = 0x0000ffff, }; /* TRSCER */ |