path: root/drivers/net/ethernet/xilinx/ll_temac.h
diff options
authorEsben Haabendal <esben@geanix.com>2020-02-21 07:47:58 +0100
committerDavid S. Miller <davem@davemloft.net>2020-02-24 10:58:48 -0800
commit1d63b8d66d146deaaedbe16c80de105f685ea012 (patch)
treed709f73201229581de0800d4bfbbf0a1fbcc3737 /drivers/net/ethernet/xilinx/ll_temac.h
parentnet: ll_temac: Fix RX buffer descriptor handling on GFP_ATOMIC pressure (diff)
net: ll_temac: Handle DMA halt condition caused by buffer underrun
The SDMA engine used by TEMAC halts operation when it has finished processing of the last buffer descriptor in the buffer ring. Unfortunately, no interrupt event is generated when this happens, so we need to setup another mechanism to make sure DMA operation is restarted when enough buffers have been added to the ring. Fixes: 92744989533c ("net: add Xilinx ll_temac device driver") Signed-off-by: Esben Haabendal <esben@geanix.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/xilinx/ll_temac.h')
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/xilinx/ll_temac.h b/drivers/net/ethernet/xilinx/ll_temac.h
index 99fe059e5c7f..53fb8141f1a6 100644
--- a/drivers/net/ethernet/xilinx/ll_temac.h
+++ b/drivers/net/ethernet/xilinx/ll_temac.h
@@ -380,6 +380,9 @@ struct temac_local {
/* DMA channel control setup */
u32 tx_chnl_ctrl;
u32 rx_chnl_ctrl;
+ u8 coalesce_count_rx;
+ struct delayed_work restart_work;
/* Wrappers for temac_ior()/temac_iow() function pointers above */