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authorRussell King <rmk+kernel@armlinux.org.uk>2019-02-08 15:35:54 +0000
committerDavid S. Miller <davem@davemloft.net>2019-02-08 23:08:39 -0800
commit417f3d08feffe3be29a5f868bcf817b476539338 (patch)
tree8f5a370029316869b163fd052a4eb3568b1ed8f7 /drivers/net/ethernet
parentnet: marvell: mvpp2: only reprogram what is necessary on mac_config (diff)
downloadlinux-dev-417f3d08feffe3be29a5f868bcf817b476539338.tar.xz
linux-dev-417f3d08feffe3be29a5f868bcf817b476539338.zip
net: marvell: mvpp2: read correct pause bits
When reading the pause bits in mac_link_state, mvpp2 was reporting the state of the "active pause" bits, which are set when the MAC is in pause mode. This is not what phylink wants - we want the negotiated pause state. Fix the definition so we read the correct bits. Tested-by: Sven Auhagen <sven.auhagen@voleatech.de> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet')
-rw-r--r--drivers/net/ethernet/marvell/mvpp2/mvpp2.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index 398328f10743..96e3f0669032 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -402,8 +402,8 @@
#define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1)
#define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2)
#define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3)
-#define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(6)
-#define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(7)
+#define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(4)
+#define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(5)
#define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11)
#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
#define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6