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authorVladimir Oltean <vladimir.oltean@nxp.com>2020-01-06 03:34:10 +0200
committerDavid S. Miller <davem@davemloft.net>2020-01-05 23:22:32 -0800
commit3a68ba6fbab786a50f380894c832bf36ba7335f3 (patch)
treeafe7ad5de7c1d41c109c902016aa62a694aa6880 /drivers/net/phy/phylink.c
parentmii: Add helpers for parsing SGMII auto-negotiation (diff)
downloadlinux-dev-3a68ba6fbab786a50f380894c832bf36ba7335f3.tar.xz
linux-dev-3a68ba6fbab786a50f380894c832bf36ba7335f3.zip
net: phylink: make QSGMII a valid PHY mode for in-band AN
QSGMII is a SerDes protocol clocked at 5 Gbaud (4 times higher than SGMII which is clocked at 1.25 Gbaud), with the same 8b/10b encoding and some extra symbols for synchronization. Logically it offers 4 SGMII interfaces multiplexed onto the same physical lanes. Each MAC PCS has its own in-band AN process with the system side of the QSGMII PHY, which is identical to the regular SGMII AN process. So allow QSGMII as a valid in-band AN mode, since it is no different from software perspective from regular SGMII. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy/phylink.c')
-rw-r--r--drivers/net/phy/phylink.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 1edca9725370..88686e0f9ae1 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -281,6 +281,7 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
switch (pl->link_config.interface) {
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_QSGMII:
phylink_set(pl->supported, 10baseT_Half);
phylink_set(pl->supported, 10baseT_Full);
phylink_set(pl->supported, 100baseT_Half);