diff options
| author |   Matt Carlson <mcarlson@broadcom.com> | 2010-11-24 08:31:45 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2010-11-24 11:06:16 -0800 |
| commit | 5093eedc8bdfd7d906836a44a248f66a99e27d22 (patch) | |
| tree | c0767ebe53f1d628b8e80d9e77d5eb7938f0dc1c /drivers/net/tg3.c | |
| parent | SELinux: indicate fatal error in compat netfilter code (diff) | |
| download | linux-dev-5093eedc8bdfd7d906836a44a248f66a99e27d22.tar.xz linux-dev-5093eedc8bdfd7d906836a44a248f66a99e27d22.zip | |
tg3: Apply 10Mbps fix to all 57765 revisions
Commit a977dbe8445b8a81d6127c4aa9112a2c29a1a008, entitled
"tg3: Reduce 57765 core clock when link at 10Mbps" needs to be applied
to all revisions of the 57765 asic rev, not just the A0 revision.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/tg3.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 30ccbb6d097a..ca6b3cbf44d5 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -7860,18 +7860,21 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) tw32(GRC_MODE, grc_mode); } - if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { - u32 grc_mode = tr32(GRC_MODE); + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { + if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { + u32 grc_mode = tr32(GRC_MODE); - /* Access the lower 1K of PL PCIE block registers. */ - val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; - tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); + /* Access the lower 1K of PL PCIE block registers. */ + val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; + tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); - val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5); - tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, - val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); + val = tr32(TG3_PCIE_TLDLPL_PORT + + TG3_PCIE_PL_LO_PHYCTL5); + tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, + val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); - tw32(GRC_MODE, grc_mode); + tw32(GRC_MODE, grc_mode); + } val = tr32(TG3_CPMU_LSPD_10MB_CLK); val &= ~CPMU_LSPD_10MB_MACCLK_MASK; |