diff options
| author |   Ping-Ke Shih <pkshih@realtek.com> | 2022-05-16 08:52:15 +0800 |
|---|---|---|
| committer |   Kalle Valo <kvalo@kernel.org> | 2022-05-17 18:32:00 +0300 |
| commit | a456021c6f1482b94dce77ebaeef77412cd37dba (patch) | |
| tree | 095783f675d34417330d123ceb5b67c546dd88a8 /drivers/net/wireless/realtek/rtw89/pci.c | |
| parent | rtw89: convert rtw89_band to nl80211_band precisely (diff) | |
| download | linux-dev-a456021c6f1482b94dce77ebaeef77412cd37dba.tar.xz linux-dev-a456021c6f1482b94dce77ebaeef77412cd37dba.zip | |
rtw89: pci: only mask out INT indicator register for disable interrupt v1
The design of INT indicator register (R_AX_PCIE_HIMR00_V1) is to reduce IO
during frequent interrupts, because it can stop chip sending interrupt to
host if we just set this indicator to 0, not all IMR(s). This indicator
register looks like a root interrupt controller of wifi chip.
However, we can't set all other IMR(s) to 0 during we are running on
interrupt service routine, or the indicator register can't reflect the
status of certain interrupt happened during this period, and then miss
some interrupts especially SER interrupt events.
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220516005215.5878-7-pkshih@realtek.com
Diffstat (limited to '')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw89/pci.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/pci.c b/drivers/net/wireless/realtek/rtw89/pci.c index 2bdce7024f25..0ef7821b2e0f 100644 --- a/drivers/net/wireless/realtek/rtw89/pci.c +++ b/drivers/net/wireless/realtek/rtw89/pci.c @@ -682,9 +682,6 @@ EXPORT_SYMBOL(rtw89_pci_enable_intr_v1); void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci) { rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, 0); - rtw89_write32(rtwdev, R_AX_HIMR0, 0); - rtw89_write32(rtwdev, R_AX_HAXI_HIMR00, 0); - rtw89_write32(rtwdev, R_AX_HIMR1, 0); } EXPORT_SYMBOL(rtw89_pci_disable_intr_v1); |