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| author |   Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2021-06-07 14:01:48 +0200 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-06-09 14:19:21 +0200 |
| commit | a3bb1d050e436e5ad301491315ea42c9ac0821c5 (patch) | |
| tree | d89b584d5d3c1bd6d3e7465fade3181697aff906 /drivers/staging/mt7621-pci/pci-mt7621.c | |
| parent | Merge tag 'iio-for-5.14a' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-next (diff) | |
| download | linux-dev-a3bb1d050e436e5ad301491315ea42c9ac0821c5.tar.xz linux-dev-a3bb1d050e436e5ad301491315ea42c9ac0821c5.zip | |
staging: mt7621-pci: make cleaner 'mt7621_pcie_enable_ports'
Function 'mt7621_pcie_enable_ports' call 'mt7621_pcie_enable_port'
for each available pcie port. Instead of having two for loops
there just move needed initialization. There is one setting
that can be removed which is the set for 'PCI_COMMAND_MASTER'
bit. Pci drivers are in charge of set that bit if is really
needed and should be not a mission of the controller to do that.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210607120153.24989-2-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to '')
| -rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index fe1945819d25..c14fc48e74fc 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -499,15 +499,18 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) /* configure class code and revision ID */ pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID, offset + RALINK_PCI_CLASS); + + /* configure RC FTS number to 250 when it leaves L0s */ + val = read_config(pcie, slot, PCIE_FTS_NUM); + val &= ~PCIE_FTS_NUM_MASK; + val |= PCIE_FTS_NUM_L0(0x50); + write_config(pcie, slot, PCIE_FTS_NUM, val); } static int mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) { struct device *dev = pcie->dev; struct mt7621_pcie_port *port; - u8 num_slots_enabled = 0; - u32 slot; - u32 val; int err; /* Setup MEMWIN and IOWIN */ @@ -518,27 +521,16 @@ static int mt7621_pcie_enable_ports(struct mt7621_pcie *pcie) if (port->enabled) { err = clk_prepare_enable(port->clk); if (err) { - dev_err(dev, "enabling clk pcie%d\n", slot); + dev_err(dev, "enabling clk pcie%d\n", + port->slot); return err; } mt7621_pcie_enable_port(port); dev_info(dev, "PCIE%d enabled\n", port->slot); - num_slots_enabled++; } } - for (slot = 0; slot < num_slots_enabled; slot++) { - val = read_config(pcie, slot, PCI_COMMAND); - val |= PCI_COMMAND_MASTER; - write_config(pcie, slot, PCI_COMMAND, val); - /* configure RC FTS number to 250 when it leaves L0s */ - val = read_config(pcie, slot, PCIE_FTS_NUM); - val &= ~PCIE_FTS_NUM_MASK; - val |= PCIE_FTS_NUM_L0(0x50); - write_config(pcie, slot, PCIE_FTS_NUM, val); - } - return 0; } |