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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-21 09:57:55 -0700
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-21 09:57:55 -0700
commitefea90a454c6bf95d489878ea366d5dff03f3fb7 (patch)
tree9eba629ea4325d67bca7e42d3fc46c346477c106 /include/asm-blackfin/mach-bf527/cdefBF52x_base.h
parentMerge branch 'audit.b43' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/audit-current (diff)
parentBlackfin arch: update boards files (diff)
downloadlinux-dev-efea90a454c6bf95d489878ea366d5dff03f3fb7.tar.xz
linux-dev-efea90a454c6bf95d489878ea366d5dff03f3fb7.zip
Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: Blackfin arch: update boards files Blackfin arch: dma add some API and cleanup bf54x DMA definition Blackfin arch: cleanup and promote the general purpose timers api to a core blackfin component Blackfin arch: add a cheesy install target Blackfin arch: add functions for converting between sclks and usecs Blackfin arch: add assembly function for doing 64bit unsigned division Blackfin arch: -mno-fdpic works Blackfin arch: use "char bfin_board_name[]" rather than "char *bfin_board_name" per discussion on lkml as the former uses less storage Blackfin arch: Fixing Bug: balance calls to get_task_mm with corresponding mmput calls Blackfin serial driver Kconfig: depend on DMA not being enabled rather than a specific DMA size Blackfin arch: Fix bug: missing CHIPID register field definition of BF54x Blackfin arch: Fix up /proc/cpuinfo so it is like everyone else Blackfin arch: Optimization - no need to make additional math here Blackfin arch: force irq_flags into the .data section Blackfin arch BF548 defconfig: enable watchdog by default Blackfin arch: add new processor ADSP-BF52x arch/mach support
Diffstat (limited to '')
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h19
1 files changed, 8 insertions, 11 deletions
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
index 5f801a0ef797..3f4de5d9d4cb 100644
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -45,8 +45,8 @@
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read16(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write16(CHIPID, val)
+#define bfin_read_CHIPID() bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
@@ -59,9 +59,8 @@
#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-/* legacy register name (below) provided for backwards code compatibility */
-#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
+#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 6))
+#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 6)), val)
#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
@@ -74,15 +73,13 @@
#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-/* legacy register name (below) provided for backwards code compatibility */
-#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
+#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 6))
+#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 6)), val)
#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-/* legacy register name (below) provided for backwards code compatibility */
-#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
+#define bfin_read_SIC_IWR(x) bfin_read32(SIC_IWR0 + (x << 6))
+#define bfin_write_SIC_IWR(x, val) bfin_write32((SIC_IWR0 + (x << 6)), val)
/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */