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| author |   Eran Ben Elisha <eranbe@mellanox.com> | 2019-10-07 10:31:42 +0300 |
|---|---|---|
| committer |   Saeed Mahameed <saeedm@mellanox.com> | 2020-01-16 14:11:19 -0800 |
| commit | 932ef155117cc5caf1108bd27664dab974ba6e89 (patch) | |
| tree | a10407615f0f9e264343fd14fd5b2cba89a9c3bb /include/linux/mlx5/driver.h | |
| parent | net/mlx5: Add structures layout for new MCAM access reg groups (diff) | |
| download | linux-dev-932ef155117cc5caf1108bd27664dab974ba6e89.tar.xz linux-dev-932ef155117cc5caf1108bd27664dab974ba6e89.zip | |
net/mlx5: Read MCAM register groups 1 and 2
On load, Driver caches MCAM (Management Capabilities Mask Register)
registers. in addition to the only MCAM register group (0) the driver
already reads, here we add support for reading groups 1 and 2.
Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to '')
| -rw-r--r-- | include/linux/mlx5/driver.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 27200dea0297..54431256af42 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -684,7 +684,7 @@ struct mlx5_core_dev { u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; - u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; + u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)]; u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; u8 embedded_cpu; |