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| author |   Shay Drory <shayd@nvidia.com> | 2021-12-12 14:51:27 +0200 |
|---|---|---|
| committer |   Saeed Mahameed <saeedm@nvidia.com> | 2022-01-06 16:22:52 -0800 |
| commit | 79b60ca83b6fa63ef307d2edcc77ee6581da8971 (patch) | |
| tree | 2b8c7b44f01ce3a88668d59fcdedeefb31683e7f /include/linux/mlx5/eq.h | |
| parent | net/mlx5: Split irq_pool_affinity logic to new file (diff) | |
| download | linux-dev-79b60ca83b6fa63ef307d2edcc77ee6581da8971.tar.xz linux-dev-79b60ca83b6fa63ef307d2edcc77ee6581da8971.zip | |
net/mlx5: Introduce API for bulk request and release of IRQs
Currently IRQs are requested one by one. To balance spreading IRQs
among cpus using such scheme requires remembering cpu mask for the
cpus used for a given device. This complicates the IRQ allocation
scheme in subsequent patch.
Hence, prepare the code for bulk IRQs allocation. This enables
spreading IRQs among cpus in subsequent patch.
Signed-off-by: Shay Drory <shayd@nvidia.com>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to '')
| -rw-r--r-- | include/linux/mlx5/eq.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/linux/mlx5/eq.h b/include/linux/mlx5/eq.h index ea3ff5a8ced3..3705a382276b 100644 --- a/include/linux/mlx5/eq.h +++ b/include/linux/mlx5/eq.h @@ -9,13 +9,13 @@ #define MLX5_NUM_SPARE_EQE (0x80) struct mlx5_eq; +struct mlx5_irq; struct mlx5_core_dev; struct mlx5_eq_param { - u8 irq_index; int nent; u64 mask[4]; - cpumask_var_t affinity; + struct mlx5_irq *irq; }; struct mlx5_eq * |