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| author |   Mark Zhang <markz@mellanox.com> | 2020-08-18 14:52:45 +0300 |
|---|---|---|
| committer |   Jason Gunthorpe <jgg@nvidia.com> | 2020-08-27 08:34:28 -0300 |
| commit | 7c4b1ab9f16732fb921b3f11cd127fa65f26ad5c (patch) | |
| tree | d8516108ca999b8c2aec2b095679865a22ed3cdf /include/linux/mlx5/mlx5_ifc.h | |
| parent | IB/mlx5: Add tx_affinity support for DCI QP (diff) | |
| download | linux-dev-7c4b1ab9f16732fb921b3f11cd127fa65f26ad5c.tar.xz linux-dev-7c4b1ab9f16732fb921b3f11cd127fa65f26ad5c.zip | |
IB/mlx5: Add DCT RoCE LAG support
When DCT QPs work in RoCE LAG mode:
1. DCT creation is allowed only when it is supported
2. The "port" of a DCT QP is assigned in a round-robin way
Link: https://lore.kernel.org/r/20200818115245.700581-3-leon@kernel.org
Signed-off-by: Mark Zhang <markz@mellanox.com>
Reviewed-by: Maor Gottlieb <maorg@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to '')
| -rw-r--r-- | include/linux/mlx5/mlx5_ifc.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index de1ffb4804d6..aee25e4fb2cc 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1430,7 +1430,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 log_bf_reg_size[0x5]; - u8 reserved_at_270[0x8]; + u8 reserved_at_270[0x6]; + u8 lag_dct[0x2]; u8 lag_tx_port_affinity[0x1]; u8 reserved_at_279[0x2]; u8 lag_master[0x1]; |