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| author |   Yuriy Kolerov <yuriy.kolerov@synopsys.com> | 2017-01-31 14:45:23 +0300 |
|---|---|---|
| committer |   Vineet Gupta <vgupta@synopsys.com> | 2017-02-06 09:37:57 -0800 |
| commit | 6f0310a126f1a46cac366327751bb7eb8941bdde (patch) | |
| tree | 09e1d9b27a23ec959ea8ed4435a4e62e79e26c83 /include/soc | |
| parent | ARCv2: intc: Set default priority for all core interrupts (diff) | |
| download | linux-dev-6f0310a126f1a46cac366327751bb7eb8941bdde.tar.xz linux-dev-6f0310a126f1a46cac366327751bb7eb8941bdde.zip | |
ARCv2: IDU-intc: Use build registers for getting numbers of interrupts
This enhancement is needed to allow masking all available common interrupts
in IDU interrupt controller in boot time since the kernel can
discover a number of them from the build register. Also now there
is no need to specify in device tree a list of used core interrupts
by IDU. E.g. before:
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
#interrupt-cells = <2>;
interrupts = <24 25 26 27 28 29 30 31>;
};
and after:
idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
interrupt-parent = <&core_intc>;
#interrupt-cells = <2>;
};
Signed-off-by: Yuriy Kolerov <yuriy.kolerov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'include/soc')
| -rw-r--r-- | include/soc/arc/mcip.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/include/soc/arc/mcip.h b/include/soc/arc/mcip.h index 4b6b489a8d7c..c2d1b15da136 100644 --- a/include/soc/arc/mcip.h +++ b/include/soc/arc/mcip.h @@ -14,6 +14,7 @@ #include <soc/arc/aux.h> #define ARC_REG_MCIP_BCR 0x0d0 +#define ARC_REG_MCIP_IDU_BCR 0x0D5 #define ARC_REG_MCIP_CMD 0x600 #define ARC_REG_MCIP_WDATA 0x601 #define ARC_REG_MCIP_READBACK 0x602 @@ -69,6 +70,22 @@ struct mcip_bcr { #endif }; +struct mcip_idu_bcr { +#ifdef CONFIG_CPU_BIG_ENDIAN + unsigned int pad:21, cirqnum:3, ver:8; +#else + unsigned int ver:8, cirqnum:3, pad:21; +#endif +}; + + +/* + * Build register for IDU contains not an actual number of supported common + * interrupts but an exponent of 2 which must be multiplied by 4 to + * get a number of supported common interrupts. + */ +#define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum)) + /* * MCIP programming model * |