diff options
author | Andi Kleen <ak@linux.intel.com> | 2016-10-05 09:53:10 -0700 |
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committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2016-10-17 13:39:47 -0300 |
commit | 1f888acd92c8f88b0ab9640cef0794bc5424c668 (patch) | |
tree | e97e1627d0a84a76b67738bad798f1ad7ae19aaf /tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json | |
parent | perf vendor events: Add SandyBridge V15 event file (diff) | |
download | linux-dev-1f888acd92c8f88b0ab9640cef0794bc5424c668.tar.xz linux-dev-1f888acd92c8f88b0ab9640cef0794bc5424c668.zip |
perf vendor events: Add WestmereEP-DP V2 event file
Add a Intel event file for perf.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-vuq872d1qdfettbbxkw74yv1@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to '')
-rw-r--r-- | tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json | 173 |
1 files changed, 173 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json new file mode 100644 index 000000000000..57b53562e2bd --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json @@ -0,0 +1,173 @@ +[ + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_LOAD_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load misses" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss large page walks" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_LOAD_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss caused by low part of address" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "SampleAfterValue": "2000000", + "BriefDescription": "DTLB second level hit" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss page walks complete" + }, + { + "EventCode": "0x8", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB load miss page walk cycles" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "DTLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB miss large page walks" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "DTLB_MISSES.PDE_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB misses casued by low part of address" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "DTLB_MISSES.STLB_HIT", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB first level misses but second level hit" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "DTLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "DTLB miss page walks" + }, + { + "EventCode": "0x49", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "DTLB_MISSES.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "DTLB miss page walk cycles" + }, + { + "EventCode": "0x4F", + "Counter": "0,1,2,3", + "UMask": "0x10", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "Extended Page Table walk cycles" + }, + { + "EventCode": "0xAE", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_FLUSH", + "SampleAfterValue": "2000000", + "BriefDescription": "ITLB flushes" + }, + { + "PEBS": "1", + "EventCode": "0xC8", + "Counter": "0,1,2,3", + "UMask": "0x20", + "EventName": "ITLB_MISS_RETIRED", + "SampleAfterValue": "200000", + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "ITLB_MISSES.ANY", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss large page walks" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x2", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "200000", + "BriefDescription": "ITLB miss page walks" + }, + { + "EventCode": "0x85", + "Counter": "0,1,2,3", + "UMask": "0x4", + "EventName": "ITLB_MISSES.WALK_CYCLES", + "SampleAfterValue": "2000000", + "BriefDescription": "ITLB miss page walk cycles" + }, + { + "PEBS": "1", + "EventCode": "0xCB", + "Counter": "0,1,2,3", + "UMask": "0x80", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" + }, + { + "PEBS": "1", + "EventCode": "0xC", + "Counter": "0,1,2,3", + "UMask": "0x1", + "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "SampleAfterValue": "200000", + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" + } +]
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