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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2018-03-15 10:44:37 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-03-21 17:35:00 +0100 |
| commit | 2b935d524d851830b68dd8c58d3098d775d6047a (patch) | |
| tree | 3a610ea9b6cf5ba661622072d55ec62a444c5551 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: sh73a0: Always use readl()/writel() (diff) | |
| download | linux-dev-2b935d524d851830b68dd8c58d3098d775d6047a.tar.xz linux-dev-2b935d524d851830b68dd8c58d3098d775d6047a.zip | |
clk: renesas: rcar-gen3: Always use readl()/writel()
The R-Car Gen3 CPG/MSSR driver (again) uses a mix of
clk_readl()/clk_writel() and readl()/writel() to access the clock
registers. Settle on the generic readl()/writel().
Cfr. commit 30ad3cf00e94f4a7 ("clk: renesas: rcar-gen3-cpg: Always use
readl()/writel()").
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions