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| author |   Stefan Popa <stefan.popa@analog.com> | 2019-06-24 18:12:12 +0300 |
|---|---|---|
| committer |   Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2019-06-26 21:24:21 +0100 |
| commit | 13a0af411a65c7cd452f03d86c7fe61e87109fa3 (patch) | |
| tree | ac8ecf36d73029821c4a55ca69fd2566377112d8 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | dt-bindings: iio: adc: Add buffered input property (diff) | |
| download | linux-dev-13a0af411a65c7cd452f03d86c7fe61e87109fa3.tar.xz linux-dev-13a0af411a65c7cd452f03d86c7fe61e87109fa3.zip | |
iio: frequency: adf4371: Add support for ADF4372 PLL
The ADF4372 is part of the same family with ADF4371, the main difference
is that it has only 3 channels instead of 4, as the frequency quadrupler
is missing. As a result, the ADF4372 allows frequencies from 62.5 MHz to
16 GHz to be generated.
Datasheet:
Link: https://www.analog.com/media/en/technical-documentation/data-sheets/adf4372.pdf
Signed-off-by: Stefan Popa <stefan.popa@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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