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| author |   Markos Chandras <markos.chandras@imgtec.com> | 2014-11-19 09:39:56 +0000 |
|---|---|---|
| committer | Markos Chandras <markos.chandras@imgtec.com> | 2015-02-17 15:37:30 +0000 |
| commit | d2e6d30ad123c81de1d8d6efa2e3e3e33c1e327b (patch) | |
| tree | 15eed1fdc2a4845ec601dec5b162b3a77778e12a /tools/perf/scripts/python/stackcollapse.py | |
| parent | MIPS: lib: memset: Add MIPS R6 support (diff) | |
MIPS: mm: page: Add MIPS R6 support
The MIPS R6 pref instruction only has 9 bits for the immediate
field so skip the micro-assembler PREF instruction if the offset
does not fit in 9 bits. Moreover, bit 30 (Pref_PrepareForStore) is
no longer valid in MIPS R6, so we change the default for all MIPS R6
processors to bit 5 (Pref_StoreStreamed).
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions