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| author |   Biju Das <biju.das@bp.renesas.com> | 2019-04-10 15:48:38 +0100 |
|---|---|---|
| committer |   Kishon Vijay Abraham I <kishon@ti.com> | 2019-04-17 14:13:08 +0530 |
| commit | f56511d0080ce33a17f7192a3f43d65e614da5cf (patch) | |
| tree | 17a84b2b4b282a4ab825ee316f1ba0a5955f0be1 /tools/perf/scripts/python/stackcollapse.py | |
| parent | phy: ti-pipe3: Fix PCIe power up sequence (diff) | |
| download | linux-dev-f56511d0080ce33a17f7192a3f43d65e614da5cf.tar.xz linux-dev-f56511d0080ce33a17f7192a3f43d65e614da5cf.zip | |
dt-bindings: phy: rcar-gen2: Add r8a77470 support
Add USB PHY support for r8a77470 SoC. Renesas RZ/G1C (R8A77470)
USB PHY is similar to the R-Car Gen2 family, but has the below
feature compared to other RZ/G1 and R-Car Gen2/3 SoCs
It has a shared pll reset for usbphy0/usbphy1 and this register
reside in usbphy0 block.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions