diff options
| author |   Anshuman Khandual <khandual@linux.vnet.ibm.com> | 2016-09-30 10:32:50 +0800 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2016-11-17 17:11:47 +1100 |
| commit | efe71a67b5aa89e0348ac862ca92a57d98d3fd8d (patch) | |
| tree | d0c2adad3c1ecb73e0ee911c3f3448ec1cdba99b /tools/testing/selftests/powerpc/dscr/dscr.h | |
| parent | powerpc/mm: Dump hash table (diff) | |
| download | linux-dev-efe71a67b5aa89e0348ac862ca92a57d98d3fd8d.tar.xz linux-dev-efe71a67b5aa89e0348ac862ca92a57d98d3fd8d.zip | |
selftests/powerpc: Add more SPR numbers, TM & VMX instructions to 'reg.h'/'instructions.h'
This patch adds SPR number for TAR, PPR, DSCR special
purpose registers. It also adds TM, VSX, VMX related
instructions which will then be used by patches later
in the series.
Now that the new DSCR register definitions (SPRN_DSCR_PRIV and
SPRN_DSCR) are defined outside this directory, use them instead.
Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'tools/testing/selftests/powerpc/dscr/dscr.h')
| -rw-r--r-- | tools/testing/selftests/powerpc/dscr/dscr.h | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/tools/testing/selftests/powerpc/dscr/dscr.h b/tools/testing/selftests/powerpc/dscr/dscr.h index a36af1b2c2bb..18ea223bd398 100644 --- a/tools/testing/selftests/powerpc/dscr/dscr.h +++ b/tools/testing/selftests/powerpc/dscr/dscr.h @@ -28,8 +28,6 @@ #include "utils.h" -#define SPRN_DSCR 0x11 /* Privilege state SPR */ -#define SPRN_DSCR_USR 0x03 /* Problem state SPR */ #define THREADS 100 /* Max threads */ #define COUNT 100 /* Max iterations */ #define DSCR_MAX 16 /* Max DSCR value */ @@ -48,14 +46,14 @@ inline unsigned long get_dscr(void) { unsigned long ret; - asm volatile("mfspr %0,%1" : "=r" (ret): "i" (SPRN_DSCR)); + asm volatile("mfspr %0,%1" : "=r" (ret) : "i" (SPRN_DSCR_PRIV)); return ret; } inline void set_dscr(unsigned long val) { - asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR)); + asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR_PRIV)); } /* Problem state DSCR access */ @@ -63,14 +61,14 @@ inline unsigned long get_dscr_usr(void) { unsigned long ret; - asm volatile("mfspr %0,%1" : "=r" (ret): "i" (SPRN_DSCR_USR)); + asm volatile("mfspr %0,%1" : "=r" (ret) : "i" (SPRN_DSCR)); return ret; } inline void set_dscr_usr(unsigned long val) { - asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR_USR)); + asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR)); } /* Default DSCR access */ |